1. Technical Field
The present disclosure relates to cache memories in general, and in particular to a method and apparatus for minimizing conflict misses in cache memories.
2. Description of Related Art
Cache misses can generally be categorized into three types, namely, cold access misses (i.e., when cache lines are first accessed), capacity misses (i.e., misses caused by demanding a cache line that was cast out previously), and conflict misses (i.e., misses caused by heavily accessed cache lines being mapped to the same set within a cache). To a certain extent, cold access misses can be reduced by hardware or software prefetching. Capacity misses can be reduced by increasing the size of a cache. Conflict misses can be reduced by using higher degrees of cache set associativity.
There is a practical upper limit to increasing set associativity due to increase in logic complexity and possible reduction in cache access speed. In addition, certain unique developments in system and application software of modern processor systems have created a source of cache conflict misses that cannot be effectively reduced by increasing the degree of cache set associativity. It turns out that many pages, whether accessed for instructions or data, have a common layout for their data structures such that when a particular datum in a page becomes more frequently accessed than others, then the data at the same relative location in many other pages (that is, with the same page offset) that use the same structural layout also experience more frequent access than others. This can happen in, for example, database applications in which layouts of memory pages and accesses are carefully managed. This phenomenon becomes a major cause of additional cache conflict misses due to the way that cache entries are addressed.
Consequently, it would be desirable to provide an improved method and apparatus for minimizing conflict misses in cache memories.